Efficient planar embedding of trees for VLSI layouts

The use of planar polygonal partitioning schemes for planar embedding of tree structures is examined. Two layout designs based on recursive square and triangular decompositions are described for trees having branching factors of k 2 and k 2 1, where k is an integer. The former design allocates the same amount of area to nodes at all levels and requires a total area linear in the number N of nodes in the tree. The latter design assigns increasing area to nodes closer to the root and requires a total area of O[N(k2/ (k 2 1))logN]. The longest interconnection has a length of O ( ~ ) in each case. 6, 1986 Academic Press, Inc.